A phase-locked loop (PLL) is used to establish and maintain a phase relationship between a generated output signal and an input reference signal. To provide such functionality, a PLL includes a variable frequency oscillator to generate the output signal and a phase detector to compare the phase of the output signal to the phase of the reference signal. Based on the comparison, the PLL adjusts the variable frequency oscillator to establish and maintain the phase relationship between the output signal and the reference signal. Once the phase relationship between the two signals becomes substantially constant in time (a result of which is that the input reference signal and the output signal frequencies are equal), the PLL is said to be “in lock.”
Often, rather than comparing the phase of the output signal directly to the phase of the reference signal, a frequency divider is used to first reduce the frequency of the output signal by a division factor to generate a comparison signal. The phase detector then compares the phase of the comparison signal to the phase of the reference signal and any adjustment needed to the variable frequency oscillator is made based on this comparison. The use of a frequency divider results in the frequency of the output signal being generated with a frequency that is multiple times greater than the frequency of the reference signal by an amount equal to the division factor.
A PLL has several figures of merit that are used to characterize its performance. Often, one of the more important PLL figures of merit is output phase noise. All ideal PLL generates an output signal with a single tone at a desired frequency. For such an ideal PLL, the spectrum of the output signal assumes the shape of an impulse. In practice, phase noise is seen in the spectrum of the output signal as random fluctuations or “skirting” around the impulse. For many applications, phase noise in the output signal can have a negative impact on performance.
In communication systems that use a PLL output signal to down-convert a signal, this phase noise can corrupt the resulting frequency translated signal. For example, in a received signal, a desired channel centered at a frequency ω0 can be spaced very close to a strong undesired channel centered at a frequency ω0−ΔΩ. To down-convert the desired channel to baseband, the PLL can be configured to provide an output signal with a frequency equal to the center frequency ω0 of the desired channel, and the two signals can be mixed.
In the ideal ease, the PLL output signal consists of a single tone, with no phase noise, at the frequency ω0, and only the desired channel is down-converted to baseband. In practice, the PLL output signal includes phase noise around the single tone at ω0. This phase noise further mixes with the received signal and, if the bandwidth of the phase noise is larger than the distance separating the two channels (i.e., larger than Δω), the strong undesired channel will be down-converted to baseband where it will interfere with the desired channel and reduce the sensitivity of the communication system.
One way in which the phase noise of a can be reduced is by increasing the frequency of the reference signal. A higher frequency reference signal allows for a smaller division factor to be used by the frequency divider, As described above, the division factor has the effect of multiplying the frequency of the reference signal to produce the output signal at a higher frequency. In the process, the phase noise of the reference signal is also multiplied. Thus, even though the reference signal is typically generated by a crystal oscillator with low phase noise, high-levels of noise multiplication due to a large division factor can still cause the reference signal phase noise to degrade the phase noise of the output signal.
Increasing the frequency of the reference signal allows for a decrease in the division factor and a corresponding decrease in phase noise from the reference signal in the output signal. At the same time, a higher frequency reference signal enables a higher loop bandwidth, which can reduce phase noise contributions from the variable frequency oscillator of the PLL in the output signal. A higher frequency reference signal can also provide for a lower quantization noise from the PLL divider (e.g., from a PLL divider implemented using a sigma-delta modulator).
To achieve a higher frequency reference signal, a crystal oscillator that produces a reference signal at a higher frequency can be used, but such a solution is typically costly. Another approach is to use a frequency doubler to increase the frequency of the reference signal by a factor of two. Conventional methods of doubling the frequency of the reference signal rely on duty-cycle correction circuits to first correct the duty-cycle of the reference signal provided by a crystal oscillator to be 50%. The duty-cycle of a signal is the percentage of a cycle of the signal in which the signal is “active” or high. The problem with duty-cycle correction circuits is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal. These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL.
In general, a crystal oscillator provides a reference signal at a stable frequency and with low levels of phase noise but often with a duty cycle that is not 50%. The duty-cycle correction circuits are used because, without a 50% duty-cycle reference signal, a frequency doubler will typically produce a frequency doubled version of the reference signal with a constant duty-cycle variation and period variation between adjacent cycles. As a result of these variations, edges (either rising or falling) of the frequency doubled reference signal that are used as reference points by a PLL phase detector to measure phase error in the PLL output signal will deviate from their ideal positions and cause a periodic inaccuracy in the measured phase error.
FIG. 1 illustrates an example frequency doubler 100 that can be used to double the frequency of a reference signal. As shown in FIG. 1, frequency doubler 100 includes a delay element 102 and an exclusive-OR gate 104. Delay element 102 is configured to delay a reference signal 106 with a stable frequency and low phase noise to produce a delayed reference signal 108. Exclusive-OR gate 104 is then configured to exclusive-OR the reference signal 106 and the delayed reference signal 108 to produce a reference signal 110 with double the frequency of reference signal 106.
A waveform diagram 112 is further provided in FIG. 1 to illustrate the operation of frequency doubler 100 when reference signal 106 does not have a 50% duty-cycle (i.e., TH/TH+TL)≠0.5). As can be seen from waveform diagram 112, when reference signal 106 does not have a 50% duty-cycle, frequency doubler 100 produces frequency doubled reference signal 110 with a constant duty-cycle variation and period variation between adjacent cycles. More specifically, between adjacent cycles 1 and 2 in frequency doubled reference signal 110, there is an apparent duty-cycle variation and period variation. This same duty-cycle variation and period variation also occurs between all other subsequent adjacent cycles, including cycles 3 and 4 and cycles 5 and 6 shown in waveform diagram 112.
The present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.